This invention relates to very large scale integrated (VLSI) circuit technology and more specifically, but not exclusively, to a method for fabricating integrated circuits (IC's) comprising metal-semiconductor field effect transistors (MESFET's).
FIG. 1 illustrates an integrated circuit comprising depletion mode n channel MESFET's 10A and 10B fabricated on a semi-insulating GaAs substrate 12. Each MESFET 10 comprises an N+source region 14 and an N+drain region 16, an N- channel 18 formed between the source and drain regions, and a source electrode 20 and a drain electrode 24 in ohmic contact with the source and drain regions respectively. A gate electrode 22 forms a rectifying junction with the channel causing an insulating depletion region to extend from the junction into the channel. Power supply 36 establishes a positive potential between the drain and source regions. When the gate potential is higher than the pinch-off voltage, electrons flow from source to drain through the channel. The MESFET shown in FIG. 1 comprises a layer 26 on the backside of channel 18. This layer has been shown to reduce short channel effects, decrease subthreshold current, increase transconductance and improve threshold voltage uniformity.
The IC shown in FIG. 1 may be fabricated by first implanting dopant, such as silicon (Si29) through a mask into the substrate 12 of semi-insulating GaAs to form the lightly doped N-type channel 18. A P-type dopant that provides shallow acceptors, such as beryllium (Be9), is implanted through the same mask to form the layer 26 on the backside of each channel. A further implantation of dopant is carried out using a mask that defines openings on either side of the channel 18 to form the N-type source and drain regions 14 and 16. In a VLSI circuit, the distance D between the MESFET'S 10A and 10B may be 3 .mu.m or less.
An IC having a high density of devices may exhibit backgating, which results in crosstalk between devices. Backgating occurs in an n channel GaAs MESFET when an ohmic-contacted region (backgate region) spaced at a small distance from an operating FET is negatively biased with respect to the source of the FET. This backgate region may be the source or drain of a nearby N channel FET. The negative bias causes carriers to leave the backgate region, travel through the region of semi-insulating substrate that separates the backgate region from the operating FET and fill the deep traps in the substrate. As the negative bias on the backgate region increases, the depletion region in the channel widens, resulting in a reduction in drain current. When the negative bias voltage reaches a certain threshold value, at which all the deep traps in the substrate are filled (trap-fill-limited-voltage), the substrate resistance decreases sharply and therefore the substrate current rises steeply. This corresponds to an equally rapid decrease in drain current.
Crosstalk between devices due to backgating is an extremely undesirable effect in an IC, and increases as the density and complexity of IC's increases. When significant backgating occurs, FET characteristics depend not only on the internal device biases but also on the proximity of negative voltage lines. Normally straightforward design considerations, such as dc operating points and matching between devices, become layout dependent, leading to severe design complications. To reduce the effects of backgating, the backgate threshold voltage (trap-fill-limited-voltage) must be decreased (more negative).
In an IC of the kind shown in FIG. 1, the backgate threshold voltage is typically about -6 v. The dopant concentration in the layer 26 on the backside of the channel has no effect on the backgate threshold voltage.
In K. Inokuchi et al "Suppression of Sidegating Effect for High Performance GaAs IC's", IEEE GaAs IC Symposium, 117 (1987) there is described a method for suppressing the backgating effect in a GaAs MESFET by inserting a negatively biased P-type region between a FET and a backgate region. This biased P-type region may effectively decrease the backgate threshold voltage but is not easily incorporated into VLSI technology. A P-type region must be implanted between each FET and each potential backgate region. Implanting the separate P-type region adds photomasking steps to the fabrication process. Also, the typical spacing between a source and the P-type region is 10 .mu.m. Therefore, in an IC having multiple FET's, the space between FET's must be approximately 20 .mu.m. Such a spacing is simply too large to be feasible in a VLSI circuit. Additionally, each P-type region must be provided with an electrode in ohmic contact with the P-type region, and a negative power supply. The increase in processing complexity and in the spacing of the FET's on the IC diminishes the effectiveness of this method as applied toward VLSI technology.
In T. Shimura et al "A Buried P-Layer Lightly Doped Drain (BPLDD) Self-Aligned GaAs MESFET", Conference on Solid State Devices and Materials, pp. 387-390 (1986) there is described a method for suppressing short channel effects in a GaAs MESFET.